Simplifying Make

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This is an attempt at simplifying make, I hope it can help anyone who struggling with the basics.

Simplifying the Makefile

The simplest form for a Makefile is:

TARGET: DEPENDENCIES
	COMMAND(S)

So, if you want to do some command or commands, give it a name (TARGET) and if the commands are dependent upon anything, list those dependencies. For example, if I wanted to compile a simple main.cpp file the command would be g++ main.cpp. I can name that command whatever I want, possibly snuka (my dog’s name). The main file in this example doesn’t require files other than itself, so the dependency list would simply be itself.

snuka: main.cpp
	g++ main.cpp

If that main file used a class I developed, such as Dog, defined in dog.cpp and dog.hpp, then my main program will depend on that class. Classes are most easily dealt with when compiled into object files such as dog.o. Make will create the dog.o file automatically (or at least try to), if I need it. So now my rule might need to be:

snuka: main.cpp dog.o
	g++ main.cpp dog.o

If I wanted to name the executable snuka, rather than a.out (the default), the rule would be:

snuka: main.cpp dog.o
	g++ main.cpp dog.o -o snuka

Thus, to build an executable file named snuka, which has a main function in main.cpp and uses code from the Dog class, I’d just need to run make snuka.